In recent years semiconductor devices in which shallow trench isolation (STI) is put to practical use have been manufactured. An n-type well region is isolated from a p-type well region by the STI.
Japanese Laid-Open Patent Publication No. 2000-012680 discloses with p-channel metal oxide semiconductors (MOSes) which are typical semiconductor elements, for example, an n-type well region is formed in a p-type silicon (Si) substrate. The n-type well region has a predetermined depth from the surface of the p-type Si substrate. An active region is formed in the n-type well region. Source/drain regions, a gate oxide film, a gate electrode, and the like are formed in the active region. By doing so, a p-channel MOS is formed.
In addition, Japanese Laid-Open Patent Publication No. 03-030468 discloses a triple well structure in which a p-type well region of a p-type silicon substrate in which an n-channel MOS transistor is formed is surrounded by an n-type well region has recently been proposed.
However, with a recent increase in the integration level of semiconductor devices there is a tendency for a space between n-type well (or p-type well) regions to become narrower. Therefore, if n-type well (or p-type well) regions differ in electric potential, then a leakage current may flow between the n-type well (or p-type well) regions. As a result, excess electric power is consumed in a semiconductor device, power supply potential drops in the semiconductor device, or latch-up is caused by the leakage current in the semiconductor device.